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Publications

Journal Articles

  1. L.L. Jiang, D. L. Maskell and J. C. Patra, “Parameter Estimation of Solar Cells and Modules using an Improved Adaptive Differential Evolution Algorithm”, Applied Energy, Vol. 112, pp. 185–193, 2013.
  2. Y. Chen, B. Schmidt and D.L. Maskell, “A hybrid short read mapping accelerator” BMC Bioinformatics, Vol. 14 (67), 2013.
  3. L.L. Jiang, D. L. Maskell and J. C. Patra, “A Novel Ant Colony Optimization-based Maximum Power Point Tracking for Photovoltaic Systems under Partially Shaded Conditions”, Energy & Buildings, vol. 58 (March 2013), pp 227–236, 2013.
  4. D. Nayanasiri, D M Vilathgamuwa and D L Maskell, "Half-Wave Cycloconverter Based Photovoltaic Microinverter Topology with Phase Shift Power Modulation," IEEE Trans. Power Electronics, vol. 28(6), pp 2700-2710, 2013.
  5. Chen Yupeng, B. Schmidt and D.L. Maskell, “A Reconfigurable Accelerator for the Word Matching Stage of BLASTN”, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol 21 (4), pp. 659 – 669, 2013.
  6. S. Chandrasekaran, S. Shanbhag, R. Jayaraman; H-Y. Cheah, and D.L. Maskell, “C2FPGA: Parallelizing HLL Applications using a Dependency-Timing Graph based Methodology”, accepted, J. Parallel and Distributed Computing, Vol. 73 (11), pp 1417–1429, 2013.
  7. R. Jayaraman and D.L. Maskell, “Temporal and spatial variations of the solar radiation observed in Singapore”, Energy Procedia, vol. 25(2012), pp 108-117, 2012.
  8. Y. Liu, B. Schmidt, D.L. Maskell, "CUSHAW: a CUDA compatible short read aligner to large genomes based on the Burrows-Wheeler transform", Bioinformatics, Vol. 28 (14), pp. 1830-1837, 2012.
  9. J.C. Patra and D.L. Maskell, “Modeling of Multi-Junction Solar cells for Estimation of EQE under Influence of Charged Particles Using Artificial Neural Networks”, Renewable Energy, vol. 44, pp 7-16, 2012.
  10. J. Cui and D.L. Maskell, “A Fast High-level Event-driven Thermal Estimator for Dynamic Thermal Aware Scheduling”, IEEE Trans. Computer-Aided Design Integr. Circuits Syst., Vol. 31(6), pp. 904-917, 2012.
  11. Y. Liu, B. Schmidt and D. L. Maskell, “Parallelized short read assembly of large genomes using de Bruijn graphs”, BMC Bioinformatics, vol. 12:354, 2011.
  12. Y. Liu, B. Schmidt and D.L. Maskell, “DecGPU: distributed error correction on massively parallel graphics processing units using CUDA and MPI”, BMC Bioinformatics, vol. 12:85, 2011.
  13. Quek, C., Guo, Z. and Maskell, D.L., “FAM-AARS: A Fuzzy Associative Memory network based on the Approximate Analogical Reasoning Schema”, Int. J. Fuzzy System Applications, vol. 1 (1), pp. 61-78, 2011.
  14. L. Kuttippurathu; M. Hsing; Y. Liu; B. Schmidt; D.L. Maskell, K. Lee; A. He; W.T. Pu; S.W. Kong, “CompleteMOTIFs: DNA motif discovery platform for transcription factor binding experiments”, Bioinformatics, Vol. 27 (5), pp. 715-717, 2011.
  15. Liu, Y., Schmidt, B. and Maskell, D.L., “MSAProbs: multiple sequence alignment based on pair hidden Markov models and partition function posterior probabilities”, Bioinformatics, Vol. 26 (16), pp. 1958–1964, 2010.
  16. Liu, Y., Schmidt, B. and Maskell, D.L., “CUDASW++2.0: enhanced Smith-Waterman protein database search on CUDA-enabled GPUs based on SIMT and virtualized SIMD abstractions”, BMC Research Notes, Vol. 3.93, 2010.
  17. Goh,G.M., Quek, C. and Maskell, D.L., "EpiList II: Closing the Loop in the Development of Generic Cognitive Skills", IEEE Trans Systems, Man and Cybernetics, Vol. 40 (4), pp. 676-685, 2010.
  18. Liu, Y., Schmidt, B., Liu, W. and Maskell, D.L., “CUDA-MEME: Accelerating Motif Discovery in Biological Sequences Using CUDA-enabled Graphics Processing Units”, Pattern Recognition Letters, Vol. 31 (14), pp 2170-2177, 2010.
  19. Vinod, A.P., Lai, E., Maskell, D.L. and P.K. Meher, “An Improved Common Subexpression Ellimination Method for Reducing Logic operators in FIR Filter Implementations without Increasing Logic Depth”, Integration, the VLSI Journal, Vol. 43 (1), pp. 124-135, 2010.
  20. Liu, Y., Maskell, D.L. and Schmidt, B., “CUDASW++: Optimizing Smith-Waterman Sequence Database Searches for CUDA-enabled Graphics Processing Units”, BMC Research Notes, Vol. 2 (73), 2009.
  21. Oliver, T.F., Schmidt, B., Jacop, Y. and Maskell, D.L., “High-Speed Biological Sequence Analysis with Hidden Markov Models on Reconfigurable Platforms”, IEEE Trans. Inf. Technol. Biomed., Vol. 13 (1), pp 740-746, 2009.
  22. Wang, Y., Maskell, D.L. and Jussipekka Leiwo, “A Unified Architecture for a Public Key Cryptographic Coprocessor”, J. Syst.Architect., Vol. 54 (10), pp. 1004-1016, 2008.
  23. Maskell, D.L., “Design of Efficient Multiplierless FIR Filters”, IET Circuits Devices Syst., Vol 1 (2), pp. 175-180, 2007.
  24. Chen, X. and Maskell, D.L., “Supporting Multiple-Input, Multiple-Output Custom Functions in Configurable Processors”, Journal of Systems Architecture, Vol. 53 (5-6), pp. 263-271, 2007.
  25. Chen, X., Maskell, D.L. and Sun, Y., “Fast Identification of Custom Instructions for Extensible Processors”, IEEE Trans. Computer-Aided Design Integr. Circuits Syst., Vol. 26 (2), pp. 359-368, 2007.
  26. Oliver, T.F. and Maskell, D.L., “Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System”, EURASIP Journal Embedded Systems, 2007.
  27. Oliver, T.F., Schmidt, B., Maskell, D.L., Nathan, D. and Clemens, R., “High-speed multiple sequence alignment on a reconfigurable platform”, Int. J. Bioinformatics Research and Applications, Vol. 2, No. 4, pp. 394-406, 2006.
  28. Maskell, D.L. and Woods, G.S., “Adaptive Subsample Delay Estimation using Windowed Correlation”, IEEE Trans. Circuits Syst. II, Vol. 53 (6), pp 478-482, 2006.
  29. Oliver, T.F., Schmidt, B. and Maskell, D.L., "Reconfigurable Architectures for Bio-sequence Database Scanning on FPGAs", IEEE Trans. Circuits Syst. II, Vol. 52, pp. 851-855, Dec, 2005.
  30. Maskell, D.L. and Liewo, J., "Hardware efficient FIR filters with a reduced adder step", IEE Electronics Letters, Vol. 41, No. 22, pp. 1211-1213, Oct., 2005.
  31. Maskell, D.L. and Woods, G.S., "Adaptive subsample delay estimation using a modified quadrature phase detector", IEEE Trans. Circuits Syst. II, Vol. 52, pp. 669-674, Oct., 2005.
  32. Oliver, T.F., Schmidt, B., Nathan, D., Clemens, R. and Maskell, D.L., “Using reconfigurable hardware to accelerate multiple sequence alignment with ClustalW”, Bioinformatics, Vol. 21, pp. 3431 – 3432, Aug., 2005.

Conference Papers (Published Proceedings)

  1. L.L. Jiang, D.R. Nayanasiri, D.L. Maskell, D.M. Vilathgamuwa, “A Simple and Efficient Hybrid Maximum Power Point Tracking Method for PV Systems under Partially Shaded Conditions”, IECON 2013, Vienna, Nov., 2013.
  2. D. Nayanasiri, D.M. Vilathgamuwa, D.L. Maskell, “High-Frequency-Link Micro-inverter with Front-end Current-fed Half-Bridge Boost converter and Half-wave Cycloconverter”, IECON 2013, Vienna, Nov., 2013.
  3. D. Nayanasiri, D.M. Vilathgamuwa, D.L. Maskell, “Current-Controlled Resonant Circuit Based Photovoltaic Micro-inverter with Half-Wave Cycloconverter”, IEEE IAS Annual Meeting, Orlando, FL., USA, Oct., 2013.
  4. D. Nayanasiri, D.M. Vilathgamuwa, D.L. Maskell, “Photovoltaic Micro-inverter with Front-end DC-DC Converter and Half-wave Cycloconverter”, ECCE Asia 2013, Melbourne, Australia, June, 2013.
  5. A.K. Jain, J. Cui, K. Pham, S.A. Fahmy and D.L. Maskell, “Virtualization of an FPGA based Hybrid Computing Platform”, IEEE Int. Conf. Application-specific Sys., Architectures and Processors (ASAP13), Washington D.C., USA, Jun., 2013.
  6. H.Y. Cheah, S.A. Fahmy and D.L. Maskell, “ iDEA: A DSP block based FPGA soft processor”, Int. Conf. Field-Programmable Technology (FPT), Seoul, Korea, Dec., 2012.
  7. Y. Chen, B. Schmidt and D L Maskell, “An FPGA aligner for short read mapping”, Int. Conf. Field Programmable Logic and Applications (FPL), Oslo, Norway, Aug., 2012.
  8. L.L. Jiang, D.L. Maskell and J.C. Patra, “Chebyshev Functional Link Neural Network-Based Modeling and Experimental Verification for Photovoltaic Arrays”, IEEE Int. Joint Conf. Neural Networks (IJCNN), Brisbane, Australia, June, 2012.
  9. L.L. Jiang, D.L. Maskell and J.C. Patra, “A FLANN-based controller for maximum power point tracking in PV systems under rapidly changing conditions, IEEE Int. Conf. Acoust., Speech, & Sig. Proc. (ICASSP), Kyoto, Japan, March 2012.
  10. Y. Chen, B. Schmidt and D.L. Maskell, “Short Read Alignment Acceleration with FPGA”, ACM Int. Symp. Field Programmable Gate Arrays (FPGA), San Jose, USA, Feb., 2012.
  11. H.Y. Cheah, S.A. Fahmy, D.L. Maskell, C. Kulkarni, “Lean FPGA Soft Processor Built Using a DSP Block”, ACM Int. Symp. Field Programmable Gate Arrays (FPGA), San Jose, USA, Feb., 2012.
  12. R. Jayaraman, H. Kartadihardja and D.L. Maskell, “Performance-power design space exploration in a hybrid computing platform suitable for mobile applications”, IEEE Int. Symp. Electronic Sys. Design, Kochi, India, December 2011.
  13. R. Jayaraman and D.L. Maskell, “Temporal and spatial variations of the solar radiation observed in Singapore”, Energy Procedia: PV Asia Pacific Conf., Singapore, Nov., 2011.
  14. Y. Liu, B. Schmidt and D.L. Maskell, "An ultrafast scalable many-core motif discovery algorithm for multiple GPUs", IEEE International Workshop on High Performance Computational Biology (HiCOMB 2011), 2011, Anchorage, Alaska.
  15. J.C. Patra, L.L. Jiang, D.L. Maskell, “Estimation of external quantum efficiency for multi-junction solar cells under influence of charged particles using artificial neural networks”, Proc. IEEE Int. Conf. Sys., Man and Cybernetics, pp 465-470, Anchorage, USA, October, 2011.
  16. J.C. Patra and D.L. Maskell, “Artificial Neural Network-based Model for Estimation of EQE of Multi-junction Solar Calls”, IEEE Photovoltaic Specialists Conference (PVSC-37), Seattle, USA, June, 2011.
  17. S. Chandrasekaran, A. Busireddy, S. Shanbhag and D.L. Maskell, “HLL mapping to FPGA using a dependency analysis based graphical methodology”, Many Core and Reconfigurable Supercomputing Conference (MRSC), Rome, March 2010.
  18. J.C. Patra and D.L. Maskell, “Estimation of Dual-Junction Solar Cell Characteristics Using Neural Networks,” IEEE Photovoltaic Specialists Conference (PVSC-35), Honolulu, USA, June 2010.
  19. S. Chandrasekaran, S. Shanbhag and D.L. Maskell, “A Dependency Graph based Methodology for Parallelizing HLL Applications on FPGA”, ACM Int. Symp. Field Programmable Gate Arrays (FPGA), 21-23 Feb., 2010.
  20. J. Cui and D.L. Maskell, “High Level Event Driven Thermal Estimation for Thermal Aware Task Allocation and Scheduling”, ASP-DAC 2010, Jan. 18-21 2010.
  21. Y. Wang and D.L. Maskell, “A Robust Algorithm for DPA-resistant ECC”, ISIC 2009, Singapore, Dec. 2009.
  22. R. Jayaraman and D.L. Maskell, “A framework for supporting hardware acceleration under operating system control”, ICITA 2009, Hanoi, Vietnam, Nov. 2009.
  23. Y. Liu, B. Schmidt and D.L. Maskell, “MSA-CUDA: Multiple Sequence Alignment on Graphics Processing Units with CUDA”, IEEE Int. Conf. Application-specific Systems, Architectures and Processors (ASAP 2009), Boston, MA, USA, July, 2009.
  24. Y. Liu, B. Schmidt and D.L. Maskell, “Parallel Reconstruction of Neighbor-Joining Trees for Large Multiple Sequence Alignments using CUDA”, IEEE Int. Workshop on High Performance Computational Biology (HiCOMB 2009), Rome, Italy, May, 2009.
  25. Y. Chen, B. Schmidt and D.L. Maskell, “A Reconfigurable Bloom Filter Architecture for BLASTN”, Architecture of Computing Systems (ARCS 2009), Delft, Netherlands, Mar., 2009.
  26. J. Cui and D.L. Maskell, “Dynamic Thermal-Aware Scheduling on Chip Multiprocessor for Soft Real-time Systems”, GLSVLSI 2009, Boston, Massachusetts, May, 2009.
  27. D.L. Maskell, A.P. Vinod and G.S. Woods, “Multiplierless Multi-Standard SDR Channel Filters”, IEEE Int. Workshop Multimedia Signal Processing (MMSP 2008), Cairns, Australia, Oct., 2008.
  28. G.S. Woods and D.L. Maskell, “Options for High Capacity Data Communications on the Great Barrier Reef”, Int. Conf. Information Technology and Applications (ICITA’08), Cairns, Australia, June 2008.
  29. S. Chandrasekaran, O.R Hernandez, D.L. Maskell, B. Chapman, and V. Bui.: “Compilation and Parallelization Techniques with Tool Support to realize Sequence Alignment Algorithm on FPGA and Multicore”, Workshop on New Horizons in Compilers, IEEE Int. Conf. on High Performance Computing (HiPC), Goa, India, 2007.
  30. A. Cai, C. Quek and D.L. Maskell, “Type-2 GA-TSK fuzzy neural network”, IEEE Congress Evolutionary Computation (CEC), pp. 1578-1585, Singapore, 2007.
  31. I.V. McLoughlin, D.L. Maskell, T. Srikanthan and W-B. Goh, “Embedded Systems graduate education for Singapore”, IEEE ICPADS 2007, Taiwan, 2007.
  32. Y.L. Aung, D.L. Maskell, T.F. Oliver, B. Schmidt, W. Bong, “C-Based Design Methodology for FPGA Implementation of ClustalW MSA”, Lecture Notes in Computer Science, Springer-Verlag, Vol. 4774, pp. 11-18, 2007.
  33. Chen, X., Maskell, D.L., and Sun, Y., “Automatic Identification of Custom Functions for Embedded Processors with MIMO Extensions”, APCCAS 2006, Singapore, 2006.
  34. Tham, K.S. and Maskell, D.L., “Software-oriented approach to Hardware-Software Co-simulation for FPGA-based RISC extensible processor”, FPL’06, Madrid, Spain, 2006.
  35. Oliver, T.F. and Maskell, D.L., “Execution Objects for Dynamically Reconfigurable FPGA Systems”, FPL’06, Madrid, Spain, 2006.
  36. Maskell, D.L., Leiwo, J. and Patra, J.C., “The Design of Multiplierless FIR Filters with a Minimum Adder Step and Reduced Hardware Complexity”, ISCAS 2006, Kos, Greece, 2006.
  37. Oliver,T.F., Schmidt, B., Yanto, J. and Maskell, D.L., “Accelerating the Viterbi Algorithm for Profile Hidden Markov Models using Reconfigurable Hardware”, Lecture Notes in Computer Science, Springer-Verlag, Vol. 3991, pp. 522-529, 2006.
  38. Chen, X. and Maskell, D.L., “M2E: A Multiple-Input, Multiple-Output Function Extension for RISC-Based Extensible Processors”, Lecture Notes in Computer Science, Springer-Verlag, Vol 3894, pp. 191-201, 2006.
  39. Oliver, T.F. and Maskell, D.L., “An FPGA Model for Developing Dynamic Circuit Computing”, IEEE Field-Programmable Technology, Singapore, Dec., 2005.
  40. Tham, K.S. and Maskell, D.L., “Software-oriented System-level simulation for Design Space Exploration of Reconfigurable Architectures”, Lecture Notes in Computer Science, Springer-Verlag, Vol 3740, pp. 391-404, 2005.
  41. Yanto, J., Oliver, T.F., Schmidt, B. and Maskell, D.L., “Biological Sequence Analysis with Hidden Markov Models on an FPGA”, Lecture Notes in Computer Science, Springer-Verlag, Vol 3740, pp. 429-439, 2005.
  42. Lee, Y.S., Oliver, T.F. and Maskell, D.L., "Reconfigurable Computing: Peripheral Power and Area Optimization Techniques", TENCON 2005, Melbourne, Australia, Nov., 2005.
  43. Oliver, T.F., Schmidt, B., Nathan, D., Clemens, R. and Maskell, D.L., “Muliptiple Sequence Alignment on an FPGA”, HiPCoMB 2005, Fukuoka, Japan, July, 2005.
  44. Oliver, T.F., Schmidt, B., Maskell, D.L. and Vinod, A.P., “A Reconfigurable Architecture for Scanning Biosequence Databases”, ISCAS 2005, Kobe, Japan, pp. 4799-4802, May, 2005.
  45. Oliver, T.F., Schmidt, B. and Maskell, D.L., “Hyper Customized Processors for Bio-Sequence Database Scanning on FPGAs”, FPGA’05, Monterey, California, Feb. 2005.
  46. Sindhwani, M., Oliver, T.F., Maskell, D.L. and Srikanthan, T., “RTOS Acceleration Techniques - Review and Challenges”, Sixth Real-Time Linux Workshop, Singapore, pp.123-128, Nov 2004.
  47. Chua, C.Y., Lim, S. and Maskell, D.L., "High Performance, Reliable and Flexible Computing Payload for Space Missions", TENCON 2004, Chiang Mai, Thailand, Nov., 2004.
  48. Woods, G.S., Maskell, D.L. and Kerans, A., "New angle-of-arrival measurement technique for over ocean propagation studies" ICCS 2004, 6-9 September, 2004, Singapore.
  49. Woods, G.S. , Kerans, A.J. and Maskell, D.L., "Simulated Angle-of-Arrival Measurements for an Over Ocean Microwave Radio Link" URSI Commission F, Triennium Open Symposium, Cairns, Australia, 1-4 June 2004.
  50. Maskell, D.L. and Woods, G.S. and Kerans, A., "A Hardware Efficient Implementation of an Adaptive Subsample Delay Estimator", ISCAS 2004, Vancouver, Canada, May, 2004.
  51. Woods, G.S., Kerans, A.J. and Maskell, D.L., "Measuring Angle-of-Arrival in Over Ocean Propagation Experiments", WARS 2004, Hobart, Australia, Feb., 2004.

Maintained by asdouglas@ntu.edu.sg
Copyright all rights reserved Doug Maskell at Nanyang Technological University.
Last modified: Mon Oct 10 15:05:01 2022 by p2002.pl on SCSE-S2020-1985