A New Impact-Ionization Current
Model Applicable to Both Bulk and SOI MOSFETs by Considering Self-Lattice-Heating
Chengqing Wei, Guan Huei See, Student Member, IEEE, Xing
Zhou, Senior Member, IEEE, and Lap Chan
IEEE Transactions on Electron Devices,
Vol.
55, No. 9, pp.
2378-2385, September 2008.
(Manuscript submitted January 23, 2008; revised
April 15, 2008.)
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Abstract
In existing impact ionization current (Isub) models for short-channel
MOSFETs, various models for the characteristic ionization length (l) or
the velocity-saturation region length (lsat) have been developed by using
the polynomial-fitting method in order to model the bias dependency of
the maximum electric field (Em) in the channel. This paper proposes
a bias-voltage and gate-length-dependent effective maximum electric field
(Em,eff) based on energy-balance equation, aimed at obtaining an accurate
expression of Em to increase the accuracy of the Isub model for deep submicron
devices. This new method overcomes the complicated modeling of l,
avoids the extraction of different fitting constants for different devices,
and enables unique extraction of the impact ionization coefficients (A
and B) for different devices. This improved model demonstrates excellent
agreements with the numerical data of nMOSFETs from a 90-nm technology
wafer file. Only one unique set of parameters is needed to fit the
data from devices with different biases and lengths for the same technology
node. Moreover, since the lattice temperature (Tl) is built in the
formulation of Em,eff, a compact Isub model with self-lattice-heating is
developed, which also accounts for the excess substrate current observed
in the SOI devices due to carrier heating in the channel.
References
-
[1] P. Su, K.-I. Goto, T. Sugii, and C. Hu, “A thermal activation view
of low voltage impact ionization in MOSFETs,” IEEE Electron Device Lett.,
vol. 23, no. 9, pp. 550–552, Sep. 2002.
-
[2] K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, “Impact ionization
MOS (I-MOS)—Part I: Device and circuit simulation,” IEEE Trans. Electron
Devices, vol. 52, no. 1, pp. 69–76, Jan. 2005.
-
[3] C. Hu, S. C. Tam, F.-C. Hsu, P.-K. Ko, T.-Y. Chan, an K. W. Terrill,
“Hot-electron induced MOSFET degradation—Model, monitor, and improvement,”
IEEE Trans. Electron Devices, vol. 32, no. 2, pp. 375–385, Feb. 1985.
-
[4] N. D. Arora and M. Sharma, “MOSFET substrate current model for circuit
simulation,” IEEE Trans. Electron Devices, vol. 38, no. 6, pp. 1392–1398,
Jun. 1991.
-
[5] W. Li, J. S. Yuan, S. Chetlur, J. Zhou, and A. S. Oates, “An improved
substrate current model for deep submicron MOSFETs,” Solid-State Electron.,
vol. 44, no. 11, pp. 1985–1988, Nov. 2000.
-
[6] H. Wong and M. C. Poon, “Approximation of the length of velocity saturation
region in MOSFET’s,” IEEE Trans. Electron Devices, vol. 44, no. 11,
pp. 2033–2036, Nov. 1997.
-
[7] J. S. Kolhatkar and A. K. Dutta, “A new substrate current model for
submicron MOSFET’s,” IEEE Trans. Electron Devices, vol. 47, no. 4, pp.
861–863, Apr. 2000.
-
[8] X. Gao, J. J. Liou, J. Bernier, and G. Groft, “An improved model for
substrate current of submicron MOSFETs,” Solid-State Electron., vol. 46,
no. 9, pp. 1395–1398, Sep. 2002.
-
[9] L.-A. Yang, Y. Hao, C.-L. Yu, and F.-Y. Han, “An improved substrate
current model for ultra-thin gate oxide MOSFETs,” Solid-State Electron.,
vol. 50, no. 3, pp. 489–495, Mar. 2006.
-
[10] S. Pin, K.-I. Goto, T. Sugii, and C. Hu, “Enhanced substrate current
in SOI MOSFETs,” IEEE Electron Device Lett., vol. 23, no.5, pp. 282–284,
May 2002.
-
[11] K. Y. Lim and X. Zhou, “An analytical effective channel-length modulation
model for velocity overshoot in submicron MOSFETs based on energy-balance
formulation,” Microel. Rel., vol. 42, pp. 1857–1864, 2002.
-
[12] M. Lundstrom, Fundamentals of carrier transport, vol. X, New York:
Addison-Wesley, 1990.
-
[13] P. K. Ko, VLSI electronics: microstructure science, vol. 18, New York:
Academic Press, 1988.
-
[14] G. H. See, X. Zhou, K. Chandrasekaran, S. B. Chiah, Z. M. Zhu, C.
Q. Wei, S. H. Lin, G. J. Zhu, and G. H. Lim, “A compact model satisfying
Gummel symmetry in higher order derivatives and applicable to asymmetric
MOSFETs,” IEEE Trans. Electron Devices, vol. 55, no. 2, pp. 624–631, Feb.
2008.
-
[15] Y.-G. Chen, S.-Y. Ma, J. B. Kuo, Z. Yu, and R. W. Dutton, “An analytical
drain current model considering both electron and lattice temperatures
simultaneously for deep submicron ultrathin SOI NMOS devices with self-heating,”
IEEE Trans. Electron Devices, vol. 42, no. 5, pp. 899–906, May 1995.
Citation
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