Proc. of the 7th MINDEF-NTU Joint R&D Seminar

Nanyang Technological University, Singapore, January 12, 1996, pp. 77-83.

GaAs high-speed device models based on the AIM-Spice Universal Model are implemented in a single-engine mixed-signal multi-level circuit simulator. The simulator can be used to analyse HBT, MESFET, and HEMT circuits, in addition to conventional silicon BJT/MOS circuits, and to predict the performance of MMIC's. Mixed analogue/digital circuits can be freely mixed and simulated at different levels with the desired accuracy. The dynamic delay model for the logic gates provides great speed advantage for simulating large GaAs digital circuits with "near analogue" accuracy..

• [1] Compound Semiconductor, Vol. 1, No. 2, Sept./Oct. 1995, p. 4.
• [2] A. Davis, "Implicit Mixed-Mode Simulation of VLSI Circuits," Ph.D. thesis, University of Rochester, New York, 1991.
• [3] K. Lee, M. Shur, T. A. Fjeldly, and T. Ytterdal, Semiconductor Device Modeling for VLSI, Prentice-Hall, 1993.
• [4] X. Zhou and T. Tang, "Multi-Level Modelling of GaAs High-Speed Digital Circuits," The EEE Journal, School of EEE, NTU, Vol. 7, No. 1, July 1995.
• [5] T. A. Fjeldly and M. Shur, "Unified CAD Models for HFETs and MESFETs," Proc. - 11th European Microwave Conference (Workshop Volume), Stuttgart, Sept. 1991, pp. 198-205.
• [6] S. I. Long and S. E. Butner, Gallium Arsenide Digital Integrated Circuit Design, McGraw-Hill, 1990, p. 326.
• [7] T. Tang and X. Zhou, "A Dynamic Delay Model for Mixed Gate/Circuit-Level Simulation of VLSI Circuits," (unpublished).
• [8] T. Tang, X. Zhou, and C. C. Jong, "Mixed-Mode Simulation of High-Speed HFET Logic Circuit," Proc. - 6th International Symposium on Integrated Circuit and Systems (ISIC-95), Singapore, Sept. 1995, pp. 510-514.