Proc. of the NSTI Nanotech 2006 (WCM-MSM2006)

Boston, MA, May 7-11, 2006, vol. 3, pp. 749-752.

Copyright Notice

© 2006 Nano Science and Technology Institute. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from Nano Science and Technology Institute.

A scalable short-channel MOSFET charge model valid for all bias regions is presented.  As the device length is reduced, long-channel intrinsic charge model cannot predict the short-channel dynamic behavior correctly.  The extrinsic capacitances, such as overlap capacitance and bias-dependent fringing capacitance, must be included in the charge model as they are comparable to the intrinsic capacitance at short-channel dimensions.  In order to ensure model scalability over geometry, short-channel effects must be included in the core charge model.  This paper extends the short-channel models, such as bulk-charge sharing and potential-barrier lowering, for charge modeling that is valid for all regions.  The model is verified by comparison with numerical simulations for three short-channel devices, 0.5, 0.25 and 0.09 um.  It is shown that the model accurately scales with the short-channel capacitances.

• [1] K. Suzuki, “Parasitic capacitance of submicrometer MOSFET’s,” IEEE Trans. Electron Devices, vol. 46, pp. 1895–1900, 1999.
• [2] D. Pattanayak, J. Poksheva, R. Downing, and L. Akers, “Fringing field effect in MOS devices,” IEEE Trans. Components, Hybrids, and Manufacturing Technology, [see also: IEEE Trans. on Components, Packaging, and Manufacturing Technology, Part A, B, C], vol. 5, pp. 127–131, 1982.
• [3] F. Pregaldiny, C. Lallement, and D. Mathiot, “A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs,” Solid-State Electron., vol. 46, pp. 2191–2198, 2002.
• [4] P. Klein, K. Hoffmann, and B. Lemaitre, “Description of the bias dependent overlap capacitance at LDD MOSFETs for circuit applications,” IEDM Tech. Dig., 1993, pp. 493–496.
• [5] L. D. Yau, “A simple theory to predict the threshold voltage of short-channel IGFET’s,” Solid-State Electron., vol. 17, pp. 1059–1063, 1974.
• [6] T. Toyabe and S. Asai, “Analytical models of threshold voltage and breakdown voltage of short-channel MOSFET’s derived from two-dimensional analysis,” IEEE Trans. Electron Devices, vol. 26, pp. 453–461, 1979.
• [7] X. Zhou and K. Y. Lim, “Unified MOSFET compact I V model formulation through physics-based effective transformation,” IEEE Trans. Electron Devices, vol. 48, pp. 887–896, 2001.
• [8] X. Zhou, S. B. Chiah, K. Chandrasekaran, G. H. See, W. Shangguan, S. M. Pandey, M. Cheng, S. Chu, and L.-C. Hsia, “Unified regional charge-based versus surface-potential-based compact modeling approaches,” Proc. NSTI Nanotech 2005, Anaheim, CA, May 2005, WCM, pp. 25–30.
• [9] T. L. Chen and G. Gildenblat, “An extended analytical approximation for the MOSFET surface potential,” Solid-State Electron., vol. 49, pp. 267–270, 2005.
• [10] Z.-H. Liu, C. Hu, J.-H. Huang, T.-Y. Chan, M.-C. Jeng, P. K. Ko, and Y. C. Cheng, “Threshold voltage model for deep-submicrometer MOSFETs,” IEEE Trans. Electron Devices, vol. 40, pp. 86–95, 1993.
• [11] G. H. See, S. B. Chiah, X. Zhou, K. Chandrasekaran, W. Shangguan, S. M. Pandey, M. Cheng, S. Chu, and L-C Hsia, “Unified regional charge-based MOSFET model calibration,” Proc. NSTI Nanotech 2005, Anaheim, CA, May 2005, WCM, pp. 143–146.
• [12] M. J. Kumar, V. Venkataraman, and S. K. Gupta, “On the parasitic gate capacitance of small-geometry MOSFETs,” IEEE Trans. Electron Devices, vol. 52, pp. 1676–1677, 2005.
• [13] C.-T. Sah, “A history of MOS transistor compact modeling,” Proc. NSTI Nanotech 2005, Anaheim, CA, May 2005, WCM, pp. 347–390.