Jointly automating neural architecture search and model compression to produce networks that fit within strict latency, memory, and energy budgets on target embedded hardware. The differentiable NAS line (LightNAS, SurgeNAS, YOSO, Double-Win NAS) reformulates architecture search as a continuous optimization over hardware cost proxies, enabling single-pass search on severely resource-constrained platforms and winning DAC Best Paper recognition in 2024. The compression line (Smart Scissor, EdgeCompress, TAB, CRIMP, Domino-Pro-Max) combines structured spatial pruning, ternary/binary/mixed-precision quantization, and hardware-aligned weight representations to shrink models for crossbar-based in-memory processors and edge SoCs. HACScale further unifies compound scaling with hardware awareness, co-optimizing depth, width, and resolution under a measured latency constraint rather than a proxy FLOPs budget.

Deploying deep neural networks on embedded and edge devices under hard latency deadlines, bridging the gap between DNN accuracy and real-time guarantees. Collate partitions inference workloads across edge-cloud boundaries using a collaborative scheduling framework with formal latency bounds. EvoLP introduces a self-evolving latency predictor that refines its own accuracy through online feedback, enabling latency-aware model compression without repeated hardware measurement. ZeroBN eliminates batch normalization layers through zerorization, pruning architectures under per-layer latency constraints derived from target device profiling. A 2024 survey of efficient deep learning infrastructure for embedded computing systems synthesizes deployment methodologies across GPU, FPGA, NPU, and microcontroller targets.

Rigorous, reproducible evaluation methodology for comparing deep learning deployments across heterogeneous edge hardware. EDLAB is a comprehensive benchmark toolkit covering GPUs, FPGAs, NPUs, and ARM-based SoCs, measuring throughput, energy efficiency, latency, and accuracy under unified workload conditions. The toolkit addresses a fundamental gap: prior edge AI evaluations were conducted on single platforms using inconsistent protocols, making cross-platform comparisons unreliable. EDLAB pairs hardware profiling with a systematic survey of efficient deep learning infrastructures, establishing empirical baselines for future architecture and compression research.

Silicon photonic interconnects using wavelength-division multiplexing and micro-ring resonators offer orders-of-magnitude bandwidth density over electrical wires, but micro-ring resonators shift resonance frequency with temperature, making thermal reliability a first-class routing objective. Routing algorithms minimize WDM contention while providing provable thermal reliability guarantees for resonator operating points (ASP-DAC Best Paper Candidate 2019, IEEE TCAD 2021). Hardware-software collaborated thermal sensing embeds micro-ring resonators as thermometers within the NoC fabric, enabling closed-loop monitoring without dedicated sensor overhead (TECS, DATE 2019). An automated optical accelerator search framework (TCAD 2023) applies NAS-style search to photonic hardware, discovering accelerator configurations with superior energy and bandwidth efficiency. MSONoC (2024) extends the design space to metasurface-assisted hybrid waveguide and free-space optical interconnects, and a 3D mesh optical NoC architecture (TCAD 2013) provides foundational topology analysis across multi-die stacks.

High-performance on-chip interconnect design and power-safe task placement for large-scale multi-core chips, treated as a unified hardware-software co-design problem. The ArSMART line extends SMART NoC to support arbitrary-turn single-cycle multi-hop traversal, proving that contention minimization dominates over hop-count reduction (DAC 2017) and yielding tight worst-case communication latency bounds (TCAD 2021). MARCO provides a task mapping and routing co-optimization framework for point-to-point NoC-based heterogeneous MPSoCs (TECS, CASES 2021), while LAMP introduces load-balanced multipath parallel transmission to raise throughput under heterogeneous traffic. MUGNoC (2023) designs a software-configured multicast-unicast-gather fabric that accelerates CNN dataflow patterns directly in the interconnect. On the dark-silicon side, FoToNoC (ASP-DAC Best Paper Candidate 2016) introduces a folded-torus topology for managing thermally constrained many-core chips, and hardware-software co-optimization frameworks enable selective core activation with DVFS to respect per-chip temperature budgets. A 2025 ML-based approach learns cache coherence traffic patterns to guide adaptive routing decisions.

Formal schedulability analysis and priority assignment algorithms for parallel real-time tasks modeled as directed acyclic graphs (DAGs), executing under federated and partitioned multi-core scheduling. Key results include a minimum WCRT bound for DAG tasks under prioritized list scheduling (EMSOFT 2022, TCAD), timing-anomaly-free dynamic scheduling for conditional DAGs (TECS, EMSOFT 2019), and locking protocols for parallel tasks sharing semaphore resources under federated scheduling (TCAD 2021). Spin-lock analysis for parallel real-time tasks establishes safe and tight bounds on blocking time under hard real-time constraints (IEEE TC 2021). The FT-DAG generator (2025) provides a full-topology benchmark tool for evaluating DAG scheduling algorithms. SAT-based application mapping on multiprocessor systems (CASES Best Paper Candidate) and schedulability analysis on reconfigurable FPGA hardware complete the formal-methods thread.