IEEE Transactions on Electron Devices, Vol. 49, No. 1, pp. 196-199, January 2002.

(Manuscript received May 1, 2001; revised July 30, 2001)

Copyright Notice

© 2002 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.

In this brief, previously-proposed one-region MOSFET drain current (I_ds) model is improved in the subthreshold modeling.  The compact model is derived based on first-principle drift-diffusion formulation with the correct drift and diffusion currents in strong inversion and subthreshold, respectively.  The new model has only one fitting parameter for subthreshold slope and can ensure excellent continuity with smooth transition from subthreshold to strong-inversion regimes, including the moderate-inversion region of growing importance for low-voltage and low-power circuits.

• [1] B. J. Sheu, D. L. Scharfetter, P. K. Ko, and M. C. Jeng, “BSIM: Berkely short-channel IGFET model for MOS transistors,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 558–565, 1987.
• [2] Y. Cheng, M.-C. Jeng, Z. Liu, J. Huang, M. Chan, K. Chen, P. K. Ko, and C. Hu, “A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation,” IEEE Trans. Electron Devices, vol. 44, pp. 277–287, Feb. 1997.
• [3] Y. Cheng, et al., BSIM3v3 Manual, CA: UC Berkeley, 1997–1998.
• [4] Y. Cheng, K. Chen, K. Imai, and C. Hu, “A unified MOSFET channel charge model for device modeling in circuit simulation,” IEEE Trans. Computer-Aided Design, vol. 17, pp. 641–644, Aug. 1998.
• [5] X. Zhou and K. Y. Lim, “Unified MOSFET compact I-V model formulation through physics-based effective transformation,” IEEE Trans. Electron Devices, vol. 48, pp. 887–896, May 2001.
• [6] Y. P. Tsividis, Operation and Modeling of the MOS Transistor, New York:  McGraw-Hill, 1987.
• [7] K. Y. Lim, “Design, modeling, and characterization of submicron MOSFETs,” Ph.D. dissertation, Nanyang Technological Univ., Singapore, 2001.
• [8] P. K. Ko, VLSI Electronics: Microstructure Science, New York: Academic, 1988, vol. 18, ch. 1.

• [13] X. Zhou, S. B. Chiah, K. Y. Lim, Y. Wang, X. Yu, S. Chwa, A. See, and L. Chan, "Technology-dependent modeling of deep-submicron MOSFET's and ULSI circuits," (Invited Paper), Proc. 6th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT-2001), Shanghai, Oct. 2001, Vol. 2, pp. 855-860.

1. [15] X. Zhou and K. Y. Lim, "De-embedding length-dependent edge-leakage current in shallow trench isolation submicron MOSFETs," Solid-State Electron., Vol. 46, No. 5, pp. 769-772, May 2002.
2. [5] X. Zhou, "Xsim: A compact model for bridging technology developers and circuit designers," (Invited Paper), Proc. 5th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2002), San Juan, Puerto Rico, Apr. 2002, pp. 710-714.
3. [5] S. B. Chiah, X. Zhou, K. Y. Lim, A. See, and L. Chan, "Physically-based approach to deep-submicron MOSFET compact model parameter extraction," Proc. 5th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2002), San Juan, Puerto Rico, Apr. 2002, pp. 750-753.
4. [10] X. Zhou, S. B. Chiah, and K. Y. Lim, "A Technology-Based Compact Model for Predictive Deep-Submicron MOSFET Modeling and Characterization," (Invited Paper), Proc. of the 6th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2003), San Francisco, CA, Feb. 2003, vol. 2, pp. 266-269.
5. [8] S. B. Chiah, X. Zhou, and K. Y. Lim, "Unified Length-/Width-Dependent Drain Current Model for Deep-Submicron MOSFETs," Proc. of the 6th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2003), San Francisco, CA, Feb. 2003, vol. 2, pp. 342-345.
6. [6] S. B. Chiah, X. Zhou, K. Chandrasekaran, K. Y. Lim, L. Chan, and S. Chu, "Threshold-Voltage-Based Regional Modeling of MOSFETs with Symmetry and Continuity," Proc. of the 7th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2004), Boston, MA, March 7-11, 2004, Vol. 2, pp. 175-178.
7. [34] Abhinav Kranti, Tsung Ming Chung, Denis Flandre, and Jean-Pierre Raskin, "Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications," Solid-State Electron., vol. 48, no. 6, pp. 947-959, 2004. 
8. [8] S. Baishya, A. Mallik, C. K. Sarkar, "A subthreshold surface potential model for short-channel MOSFET taking into account the varying depth of channel depletion layer due to source and drain junctions," IEEE Trans. Electron Devices, vol. 53, no. 3, pp. 507-514, Mar. 2006. 
9. [6] A. Pouydebasque, C. Charbuillet,  R. Gwoziecki, and T. Skotnicki, "Refinement of the subthreshold slope modeling for advanced bulk CMOS devices," IEEE Trans. Electron Devices, vol. 54, no. 10, pp. 2723-2729, Oct. 2007.