De-embedding Length-Dependent
Edge-Leakage Current in Shallow Trench Isolation Submicron MOSFETs
Xing Zhou and Khee Yong Lim
Solid-State Electronics,
Vol. 46, No. 5, pp. 769-772, May 2002.
(Manuscript received 19 December 2000; received in revised form 26
June 2001.)
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Abstract
A simple method is presented to de-embed the edge-leakage current in
shallow trench isolation (STI) submicron MOSFETs from the measured terminal
current. The extremely nonlinear and length-/bias-dependent "subthreshold
hump" has been modeled by a one-piece compact model using a two-step extraction
procedure, which demonstrated excellent prediction to the measurement data.
The result also suggests that the edge leakage exhibits a similar current-voltage
characteristics as the main MOSFET on the same wafer which, if not modeled
as a separate parasitic transistor, would lead to wrong information on
the main transistor's subthreshold slope.
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Citation
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[15] X. Zhou, S. B. Chiah, K.
Y. Lim, Y. Wang, X. Yu, S. Chwa, A. See, and L. Chan, "Technology-dependent
modeling of deep-submicron MOSFET's and ULSI circuits," (Invited Paper),
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[] V. Re, M. Manghisoni, L. Ratti, V. Speziali, and G. Traversi,
"Impact of lateral isolation oxides on radiation-induced noise degradation
in CMOS technologies in the 100-nm regime," IEEE Trans. Nuclear Sci., Vol.
54, No. 6, pp. 2218-2226, Dec. 2007.