Presentations

Slides(click here for the index of presentation slides)

Conference

1. "Physics-Based Compact Variability/Reliability Modeling for Emerging Double-Gate/Nanowire MOSFETs," (Invited Talk), 2011 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC2011), Tianjin, China, Nov. 17, 2011.

 
2. "Physics-Based Compact Variability/Reliability Modeling for Emerging Double-Gate/Nanowire MOSFETs," (Invited Talk), the 9th International Conference on ASIC (ASICON2011), Xiamen, China, Oct. 28, 2011.

 
3. "Statistical Compact Modeling for Emerging Nanowire / FinFET Mismatch and Variance Studies," (Invited Paper), Proc. of the 6th International Conference on Materials for Advanced Technologies (ICMAT2011), Symposium W: Reliability and Variability of Emerging Devices for Future Technologies and ULSI Circuits and Systems, Singapore, June 30, 2011.

 
4. "Xsim: A Unified Compact Model for Bulk/SOI/DG/GAA MOSFETs," (Invited Paper), the NSTI Nanotech 2011 (WCM-Nanotech2011), Boston, MA, June 15, 2011.

 
5. "Neutral Interface Traps for Negative Bias Temperature Instability," 2011 IEEE Reliability Physics Symposium (IRPS2011), Monterey, CA, Apr. 13, 2011.

 
6. "Challenges and Trends in Unified Compact Modeling of Conventional (Bulk/SOI) and Emerging (Multigate/Nanowire) MOSFETs," (Keynote), International Symposium on Next-Generation Electronics (ISNE2010), Kaohsiung, Taiwan, Nov. 18, 2010.

 
7. "A Unified Compact Model for Emerging DG FinFETs and GAA Nanowire MOSFETs Including Long/Short-Channel and Thin/Thick-Body Effects," (Invited Paper), the 10th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT2010), Shanghai, China, Nov. 2, 2010.

 
8. "Xsim: Benchmark Tests for the Unified DG/GAA MOSFET Compact Model," the NSTI Nanotech 2010 (WCM-Nanotech2010), Anaheim, CA, June 23, 2010.

 
9. "Subcircuit Approach to Inventive Compact Modeling for CMOS Variability and Reliability," the 12th International Symposium on Integrated Circuits, Devices & Systems (ISIC2009), Singapore, Dec. 15, 2009.

 
10. "Unification of MOSFET Compact Models with the Unified Regional Modeling Approach," (Invited Talk), MOS-AK Workshop, Baltimore, MD, Dec. 9, 2009.

 
11. "Unified Compact Modeling for Bulk/SOI/FinFET/SiNW MOSFETs," (Invited Paper), the 2nd International Workshop on Electron Devices and Semiconductor Technology (IEDST2009), Mumbai, India, June 2, 2009.

 
12. "Compact Model Application to Statistical/Probabilistic Technology Variations," the 12th International Conference on Modeling and Simulation of Microsystems (WCM-Nanotech2009), Houston, TX, May 6, 2009.

 
13. "New Properties and New Challenges in MOS Compact Modeling," the 11th International Conference on Modeling and Simulation of Microsystems (WCM-Nanotech2008), Boston, MA, June 3, 2008.

 
14. "New Challenges in MOS Compact Modeling for Future Generation CMOS," (Invited Paper), the 2008 IEEE International Nanoelectronics Conference (INEC2008), Shanghai, China, March 27, 2008.

 
15. "Unified Compact Modeling of Emerging Multiple-Gate MOSFETs," (Invited Paper), the 2007 International Workshop on Electron Devices and Semiconductor Technology (IEDST2007), Beijing, China, June 4, 2007.

 
16. "Unified Compact Model for Generic Double-Gate MOSFETs," (Invited Paper), Workshop on Compact Modeling, the 10th International Conference on Modeling and Simulation of Microsystems at NSTI Nanotech 2007 (WCM-Nanotech2007), Santa Clara, CA, May 22, 2007.

 
17. "Towards Unification of MOS Compact Models with the Unified Regional Approach," (Invited Paper), the 8th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT2006), Shanghai, China, Oct. 24, 2006.

 
18. "Unified Approach to Bulk/SOI/UTB/s-DG MOSFET Compact Modeling," (Invited Paper), Workshop on Compact Modeling, the 9th International Conference on Modeling and Simulation of Microsystems at NSTI Nanotech 2006 (WCM-MSM2006), Boston, MA, May 9, 2006.

 
19. "Extraction of physical parameters of strained-silicon MOSFETs from C-V measurement," the 2005 European Solid-State Device Research Conference (ESSDERC2005), Grenoble, France, September 15, 2005.

 
20. "A Compact Model for Future Generation Predictive Technology Modeling and Circuit Simulation," (Invited Paper), the 12th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES2005), Kraków, Poland, June 23, 2005.

 
21. "Unified Regional Charge-based Versus Surface-potential-based Compact Modeling Approaches," (Invited Paper), Workshop on Compact Modeling, the 8th International Conference on Modeling and Simulation of Microsystems at NSTI Nanotech 2005 (WCM-MSM2005), Anaheim, CA, May 10, 2005.

 
22. "Unified Regional Charge Model with Non-pinned Surface Potential," (Invited Paper), 2nd International Workshop on Compact Modeling (IWCM-2005) at the Asia and South Pacific Design Automation Conference (ASP-DAC2005), Shanghai, January 20, 2005.

 
23. "Xsim: Unified Regional Approach to Compact Modeling for Next Generation CMOS," (Invited Paper), the 7th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT-2004), Beijing, October 19, 2004.

 
24. "Unified Regional Approach to Consistent and Symmetric DC/AC Modeling of Deep-Submicron MOSFETs," (Invited Paper), Workshop on Compact Modeling, the 7th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2004), Boston, MA, March 9, 2004.

 
25. "A Technology-Based Compact Model for Predictive Deep-Submicron MOSFET Modeling and Characterization," (Invited Paper), Workshop on Compact Modeling, the 6th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2003), San Francisco, CA, February 25, 2003.

 
26. "Mixed-Signal Multi-Level Circuit Simulation: An Implicit Mixed-Mode Solution," (Invited Plenary Paper), (IEEE EDS Distinguished Lecturer Program), the 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES2002), Wroclaw, Poland, June 21, 2002.

 
27. "Multi-Level Modeling of Deep-Submicron MOSFETs and ULSI Circuits," (Invited Paper), the 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES2002), Wroclaw, Poland, June 20, 2002.

 
28. "Xsim: A Compact Model for Bridging Technology Developers and Circuit Designers," (Invited Paper), Workshop on Compact Modeling, the 5th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2002), San Juan, Puerto Rico, April 24, 2002.

 
29. "Technology-Dependent Modeling of Deep-Submicron MOSFET's and ULSI Circuits," (Invited Paper), the 6th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT-2001), Shanghai, October 23, 2001. 

 
30. "Semi-Empirical Approach to Modeling Reverse Short-Channel Effect in Submicron MOSFET's," the 4th International Conference on Modeling and Simulation of Microsystems (MSM2001), Hilton Head Island, SC, March 20, 2001.

 
31. "Experimental Determination of Electrical, Metallurgical, and Physical Gate Lengths of Submicron MOSFET's," the 4th International Conference on Modeling and Simulation of Microsystems (MSM2001), Hilton Head Island, SC, March 19, 2001. 

 
32. "Hetero-Material Gate Field-Effect Transistors (HMGFET's)," Invited Talk (IEEE EDS Distinguished Lecturer Program), Bluetooth Technology: Devices and Processes for a Wireless World, IEEE EDS Santa Clara Valley Chapter, Santa Clara, CA, March 16, 2001. 

 
33. "Mixed-Signal Multi-Level Circuit Simulation: An Implicit Mixed-Mode Solution," Invited Talk (IEEE EDS Distinguished Lecturer Program), National Seminar on VLSI: Systems, Design and Technology (VSDT2000), Indian Institute of Technology, Bombay, December 10, 2000.

 
34. "A Novel Approach to Compact I-V Modeling for Deep-Submicron MOSFET's Technology Development with Process Correlation," the 3rd International Conference on Modeling and Simulation of Microsystems (MSM2000), San Diego, CA, March 29, 2000. 

 
35. "A Compact MOSFET I_ds Model for Channel-Length Modulation Including Velocity Overshoot," the 1999 International Semiconductor Device Research Symposium (ISDRS-99), Charlottesville, VA, December 2, 1999. 

 
36. "Analytic Model for Currents in Si/SiGe HBT with Heavy-doping SiGe Base," the 8th International Symposium on IC Technology, Systems & Applications (ISIC-99), Singapore, September 10, 1999.

 
37. "A Predictive Length-Dependent Saturation Current Model Based on Accurate Threshold Voltage Modeling," the 2nd International Conference on Modeling and Simulation of Microsystems (MSM99), San Juan, Puerto Rico, April 21, 1999. 

 
38. "Process-Dependent MOS Threshold Voltage Formulation Based on 2-D Process and Device Simulations," the 7th International Symposium on IC Technology, Systems & Applications (ISIC-97), Singapore, September 11, 1997.

(Session Chairs for Device & IC Technology (II) - Modeling, Device & IC Technology (III) - Device Physics, and Device & IC Technology (V) - Compound Semiconductors.)
 
39. "A Dynamic Timing Delay for Accurate Gate-Level Circuit Simulation," the 39th Midwest Symposium on Circuits and Systems (MWSCAS-96), Ames, Iowa, August 19, 1996.

 
40. "Modelling and Simulation of GaAs High-Speed HEMT, HBT, and MESFET Analogue/Digital Circuits," the 7th MINDEF-NTU Joint R&D Seminar, Nanyang Technological University, Singapore, January 12, 1996.

 
41. "Monte Carlo Calculation of Base Transit Times in Ballistic-Base vs. Graded-Base HBTs," the 5th International Symposium on IC Technology, Systems & Applications (ISIC-93), Singapore, September 17, 1993. 

 
42. "Ensemble Monte Carlo Modeling of III-V Compound Semiconductors," IEEE 13th Annual Electron Device Activities in Western New York Conference, Rochester, NY, December 11, 1989.

 
43. "Monte Carlo Studies of Electron Transport in III-V Compound Heterostructure Devices," IEEE 11th Annual Electron Device Activities in Western New York Conference, Rochester, NY, November 17, 1987.

1. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," Invited Talk (IEEE EDS Distinguished Lecture Program), Institute of Microelectronics, CAS, China, November 15, 2011.

 
2. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," Invited Talk (IEEE EDS Distinguished Lecture Program), Xiamen University, Xiamen, China, October 26, 2011.

 
3. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," Invited Talk (IEEE EDS Distinguished Lecture Program), Tokyo Institute of Technology, Yokohama, Japan, Aug. 26, 2011.

 
4. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," IEEE EDS WIMNACT-29, National Chiao Tung University, Hsinchu, May 27, 2011.

 
5. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," Invited Talk (IEEE EDS Distinguished Lecture Program), Rochester Institute of Technology, Rochester, May 12, 2011.

 
6. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," IEEE EDS WIMNACT-26, Tianjin University, Tianjin, China, Dec. 29, 2010.

 
7. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," IEEE EDS WIMNACT-25, Monash University, Melbourne, Australia, Aug. 2, 2010.

 
8. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," IEEE EDS WIMNACT-25, Australian National University, Canberra, Australia, July 30, 2010.

 
9. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," IEEE EDS WIMNACT-25, University of Western Australia, Perth, Australia, July 28, 2010.

 
10. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," Invited Talk (IEEE EDS Distinguished Lecture Program), UC San Diego, June 25, 2010.

 
11. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," Invited Talk (IEEE EDS Distinguished Lecture Program), Dalian, China, June 11, 2010.

 
12. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," Invited Talk (IEEE EDS Distinguished Lecture Program), Chinese University of Hong Kong, May 20, 2010.

 
13. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," IEEE EDS WIMNACT-23, Heritage Institute of Technology, Kolkata, India, April 9, 2010.

 
14. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," IEEE EDS WIMNACT-23, National Institute of Technology, Silchar, India, April 8, 2010.

 
15. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," IEEE EDS WIMNACT-23, North Eastern Hill University, Shillong, India, April 5, 2010.

 
16. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," IEEE EDS WIMNACT-23, Indian Institute of Technology, Guwahati, India, April 2, 2010.

 
17. "Unified Regional Modeling Approach to MOS Compact Modeling," IEEE EDS WIMNACT-21, Peking and Tsinghua Universities Student Branch Chapters, Beijing, January 7, 2010.

 
18. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," Invited Talk (IEEE EDS Distinguished Lecture Program), AP/ED/MTT/SSC Penang Chapter, Penang, Malaysia, December 22, 2009.

 
19. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," Invited Talk (IEEE EDS Distinguished Lecture Program), Xidian University, Xi'an, September 1, 2009.

 
20. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," Invited Talk (IEEE EDS Distinguished Lecture Program), University of Electronic Science and Technology of China, Chengdu, August 24, 2009.

 
21. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," IEEE EDS WIMNACT-19, Bangladesh, June 6, 2009.

 
22. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," IEEE EDS WIMNACT-18, Mysore, June 4, 2009.

 
23. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," IEEE EDS WIMNACT-18, Bangalore, June 3, 2009.

 
24. "Unified Compact Modeling of Emerging Multiple-Gate MOSFETs," Invited Talk (IEEE EDS Distinguished Lecture Program), Guangzhou, September 24, 2008.

 
25. "Unified Compact Modeling of Emerging Multiple-Gate MOSFETs," Invited Talk (IEEE EDS Distinguished Lecture Program), Sematech, Austin, TX, August 7, 2008.

 
26. "Unified Compact Modeling of Emerging Multiple-Gate MOSFETs," Invited Talk (IEEE EDS Distinguished Lecture Mini-colloquium), 15th Workshop and IEEE EDS Mini-colloquium on NAnometer CMOS Technology (WIMNACT-HZ), Hangzhou, China, March 28, 2008.

 
27. "Unified Compact Modeling of Emerging Multiple-Gate MOSFETs," Invited Talk (IEEE EDS Distinguished Lecture Mini-colloquium), 15th Workshop and IEEE EDS Mini-colloquium on NAnometer CMOS Technology (WIMNACT-SH), Shanghai, China, March 24, 2008.

 
28. "Unified Compact Modeling of Emerging Multiple-Gate MOSFETs," Invited Talk (IEEE EDS Distinguished Lecture Program), Rochester Institute of Technology, Rochester, NY, December 20, 2007.

 
29. "Unified Compact Modeling of Emerging Multiple-Gate MOSFETs," Invited Talk (IEEE EDS Distinguished Lecture Program), University of Toronto, Canada, December 5, 2007.

 
30. "Unified Compact Modeling of Multiple-Gate MOSFETs," IEEE EDS WIMNACT-13, Singapore, July 25, 2007.

 
31. "Unified Compact Modeling of Multiple-Gate MOSFETs," IEEE EDS WIMNACT-13, Hong Kong, July 23, 2007.

 
32. "Unified Compact Modeling of Multiple-Gate MOSFETs," IEEE EDS WIMNACT-12 at IEDST2007, Beijing, June 4, 2007.

 
33. "A Compact Model for Future Generation Predictive Technology Modeling and Circuit Simulation," IEEE EDS Distinguished Lecture at MIXDES2005, Kraków, Poland, June 23, 2005.

 
34. "The Missing Link to Seamless Simulation," Invited Talk (IEEE EDS Distinguished Lecture Program), Fudan University, Shanghai, January 20, 2005.

 
35. "Technology-Based Predictive Compact Model Development for Next Generation CMOS," Invited Talk (IEEE EDS Distinguished Lecturer Program), CEC Huada Electronic Design Co., Ltd., Beijing, September 22, 2004.

 
36. "Technology-Based Predictive Compact Model Development for Next Generation CMOS," Invited Talk (IEEE EDS Distinguished Lecture Mini-colloquium), 5th Workshop and IEEE EDS Mini-colloquium on NAnometer CMOS Technology (WIMNACT-HK), Hong Kong, September 18, 2004.

 
37. "Technology-Based Predictive Compact Model Development for Next Generation CMOS," Invited Talk (IEEE EDS Distinguished Lecture Mini-colloquium), 4th Workshop and IEEE EDS Mini-colloquium on NAnometer CMOS Technology (WIMNACT04), Singapore, July 12, 2004.

 
38. "The Missing Link to Seamless Simulation," Invited Talk (IEEE EDS Distinguished Lecture Mini-colloquium), 3rd Workshop and IEEE EDS Mini-colloquium on NAnometer CMOS Technology (WIMNACT-Singapore), Singapore, October 15, 2003.

 
39. "Multi-Level Modeling of Deep-Submicron CMOS ULSI Systems," Invited Talk (IEEE EDS Distinguished Lecturer Program), Institute of Microelectronics, Tsinghua University, Beijing, December 13, 2002.

 
40. "Multi-Level Modeling of Deep-Submicron CMOS ULSI Systems," Invited Talk (IEEE EDS Distinguished Lecturer Program), Microelectronics R&D Center, Chinese Academy of Sciences, Beijing, December 13, 2002.

 
41. "MOSFET Compact I-V Modeling for Deep-Submicron Technology Development," Invited Talk (IEEE EDS Distinguished Lecturer Program), Wuxi Microelectronics R&D Center, Wuxi, October 24, 2001.

 
42. "MOSFET Compact I-V Modeling for Deep-Submicron Technology Development," Invited Talk (IEEE EDS Distinguished Lecturer Program), Fudan University, Shanghai, October 18, 2001.

 
43. "MOSFET Compact I-V Modeling for Deep-Submicron Technology Development," Invited Talk (IEEE EDS Distinguished Lecturer Program), Indian Institute of Technology, Bombay, December 9, 2000. 

 
44. "Subpicosecond Electrical Pulse Generation by Nonuniform Gap Illumination," Invited Talk (IEEE EDS Distinguished Lecturer Program), Beijing Vacuum Electronics Research Institute, Beijing, September 8, 2000.

 
45. "MOSFET Compact I-V Modeling for Deep-Submicron Technology Development," Invited Talk (IEEE EDS Distinguished Lecturer Program), Institute of Microelectronics, Tsinghua University, Beijing, September 6, 2000. 

1. "Xsim: A Unified Compact Model for Bulk/SOI/DG/GAA MOSFETs," Invited Talk, Fudan University, Shanghai, China, Nov. 1, 2011.

 
2. "Compact Model Application to Statistical Variability and Reliability Studies," Invited Talk, Tokyo Institute of Technology, Yokohama, Japan, Aug. 29, 2011.

 
3. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," Invited Talk, Fudan University, Shanghia, April 27, 2011.

 
4. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," Invited Talk, Hewlett-Packard, Singapore, Feb. 28, 2011.

 
5. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," Invited Talk, Institute of Microelectronics, Tsinghua University, Beijing, China, Jan. 5, 2011.

 
6. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," Invited Talk, SMIC, Shanghai, China, Nov. 3, 2010.

 
7. "Xsim: Unified Compact Model for Future Generation MultiGate MOSFETs," Compact Model Council: Multigate Compact Model Standardization, Kyoto, Japan, Mar. 18, 2010.

 
8. "Unified Regional Modeling Approach to MOS Compact Modeling," Invited Talk, Silterra Malaysia Sdn. Bhd., Malaysia, Dec. 23, 2009.

 
9. "Unification of MOS Compact Models with the Unified Regional Modeling Approach," Invited Talk, Globalfoundries, Sunnyvale, CA, Dec. 10, 2009.

 
10. "Compact Model Application to Statistical/Probabilistic Technology Variations," Invited Talk, 2nd IITB-NTU Workshop, Indian Institute of Technology - Bombay, Mumbai, Nov. 20, 2009.

 
11. "Mixed-Signal Multi-Level Circuit Simulation: An Implicit Mixed-Mode Solution," Research Seminar, Technical University of Munich, Germany, October 13, 2009.

 
12. "Compact Model Application to Statistical/Probabilistic Technology Variations," Invited Talk, Technical University of Munich, Germany, October 13, 2009.

 
13. "Unified Multi-Level Modeling for Future CMOS Technology Generations," Research Seminar, Technical University of Munich, Germany, October 12, 2009.

 
14. "Compact Model Application to Statistical and Probabilistic Technology Variations," Invited Talk, Workshop on Sustainable Nanoelectronics and Information Technology, Rice Univ., Houston, TX, June 24, 2009.

 
15. "MOSFET Comact Modeling: History, Essentials, Challenges, and Outlook," Special Technical Seminar, Mediateck Singapore Pte Ltd, April 9, 2009.

 
16. "MOS Compact Modeling: History, Fundamentals, and Outlook," Distinguished Guest Speaker, Chartered TD/ACT Tech Forum, Singapore, November 21, 2008.

 
17. "Xsim: Unified Compact Model for Future Generation CMOS," Compact Model Council: Next Generation SOI MOSFET Compact Models, Boston, MA, June 5, 2008.

 
18. "New Challenges in MOS Compact Modeling for Future Generation CMOS," Invited Talk, Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, Switzerland, March 11, 2008.

 
19. "New Challenges in MOS Compact Modeling for Future Generation CMOS," Invited Talk, University of Rochester, December 19, 2007.

 
20. "Silicon Nanowire Modeling Research," 2nd Workshop on Future ICs - A CINTRA Workshop, jointly organized by CNRS-IEMN, Thales, and NTU, Institute of Electronics Microelectronic and Nanotechnology (IEMN), France, October 18, 2007.

 
21. "Compact Modeling: Computational Investigation of Novel Device Structures and Concepts using TCAD," Invited Short Course, Faculty of Electrical Engineering, Universiti Teknologi Malaysia, Malaysia, May 18, 2007.

 
22. "Compact Modeling: Parameter Extraction and Circuit Simulation," Invited Short Course, Faculty of Electrical Engineering, Universiti Teknologi Malaysia, Malaysia, May 17, 2007.

 
23. "Compact Modeling: Formulation and Characterization," Invited Short Course, Faculty of Electrical Engineering, Universiti Teknologi Malaysia, Malaysia, May 16, 2007.

 
24. "Compact Modeling: Overview, Introduction and Basic Concepts," Invited Short Course, Faculty of Electrical Engineering, Universiti Teknologi Malaysia, Malaysia, May 15, 2007.

 
25. "Unified Regional Approach to MOS Transistor Compact Modeling for Circuit Simulation," Invited Talk, Altera Corp., San Jose, CA, August 11, 2006.

 
26. "Towards Unification of MOSFET Compact Models with the Unified Regional Approach," Invited Talk, Advanced Micro Devices, Sunnyvale, CA, August 11, 2006.

 
27. "Towards Unification of MOSFET Compact Models with the Unified Regional Approach," Invited Talk, Cadence Design Systems, San Jose, CA, August 9, 2006.

 
28. "Technology-Based Predictive Compact Model Development for Next Generation CMOS," Invited Talk, Advanced Micro Devices, Sunnyvale, CA, December 18, 2004.

 
29. "Technology-Based Predictive Compact Model Development for Next Generation CMOS," Invited Talk, Silicon Storage Technology, Sunnyvale, CA, December 10, 2004.

 
30. "Mixed-Signal Multi-Level Circuit Simulation: An Implicit Mixed-Mode Solution," Invited Talk, Intel Corp., Santa Clara, CA, February 28, 2003.

 
31. "Mixed-Signal Multi-Level Circuit Simulation: An Implicit Mixed-Mode Solution," Invited Talk (COE Visiting Professor), Research Center for Nanodevices and Systems, Hiroshima University, Japan, January 28, 2003.

 
32. "MOSFET Compact I-V Modeling for Deep-Submicron Technology Development," Invited Talk (COE Visiting Professor), Research Center for Nanodevices and Systems, Hiroshima University, Japan, January 21, 2003.

 
33. "MOSFET Compact I-V Modeling for Deep-Submicron Technology Development," Invited Talk, Swiss Federal Institute of Technology - Lausanne (EPFL), Lausanne, Switzerland, June 17, 2002.

 
34. "Mixed-Signal Multi-Level Circuit Simulation: An Implicit Mixed-Mode Solution," Invited Talk, Motorola, Geneva, Switzerland, June 17, 2002.

 
35. "MOSFET Compact I-V Modeling for Deep-Submicron Technology Development," Invited Talk, LSI Logic Corp., Santa Clara, CA, April 18, 2002.

 
36. "MOSFET Compact I-V Modeling for Deep-Submicron Technology Development," Invited Talk, Intel Corp., Santa Clara, CA, April 17, 2002.

 
37. "MOSFET Compact I-V Modeling for Deep-Submicron Technology Development," Invited Talk, Advanced Micro Devices, Inc., Sunnyvale, CA, April 16, 2002.

 
38. "MOSFET Compact I-V Modeling for Deep-Submicron Technology Development," Visiting Researcher Seminar, LSI Logic Corp., Santa Clara, CA, March 26, 2001.

 
39. "MOSFET Compact I-V Modeling for Deep-Submicron Technology Development," Invited Talk, Electrical Engineering Department, University of California at Berkeley, March 22, 2001.

 
40. "MOSFET Compact I-V Modeling for Deep-Submicron Technology Development," Invited Talk, Center for Integrated Systems, Stanford University, March 2, 2001.

 
41. "Unified MOSFET Compact Model Formulation for Deep-Submicron Technology Development and Multi-Level Circuit Simulation," Invited Talk, LSI Logic Corp., Santa Clara, CA, March 24, 2000.

 
42. "Unified MOSFET Compact Model Formulation for Deep-Submicron Technology Development and Multi-Level Circuit Simulation," Invited Talk, Maxim Integrated Products, Inc., Sunnyvale, CA, March 23, 2000.

 
43. "Unified MOSFET Compact Model Formulation Through Physics-Based Effective Transformation for Multi-Level Technology Modeling and Circuit Design,".Research Seminar, Department of Electrical and Computer Engineering, University of Rochester, NY, December 17, 1999.

 
44. "Unified MOSFET Compact Model Formulation Through Physics-Based Effective Transformation for Multi-Level Technology Modeling and Circuit Design,".Research Seminar, Eastman Kodak Co., Rochester, NY, December 17, 1999.

 
45. "Unified MOSFET Compact Model Formulation Through Physics-Based Effective Transformation for Multi-Level Technology Modeling and Circuit Design,".Research Seminar, LSI Logic Corp., Fairport, NY, December 16, 1999.

 
46. "Unified MOSFET Compact Model Formulation Through Physics-Based Effective Transformation for Multi-Level Technology Modeling and Circuit Design,".Research Seminar, McMaster University, Canada, December 13, 1999.

 
47. "A Novel Approach to Compact I-V Modeling for Deep-Submicron MOSFET's Technology Development," Invited Talk, Intel Corp., Santa Clara, CA, April 23, 1999.

 
48. "Exploring the Novel Characteristics of Hetero-Material Gate Field-Effect Transistors (HMGFET's) with Gate Material Engineering," Invited Talk, Intel Corp., Portland, OR, June 25, 1998.

 
49. "Exploring the Novel Characteristics of Hetero-Material Gate Field-Effect Transistors (HMGFET's) with Gate Material Engineering," Invited Talk, IBM T. J. Watson Research Center, Yorktown Heights, NY, June 19, 1998.

 
50. "Exploring the Novel Characteristics of Hetero-Material Gate Field-Effect Transistors (HMGFET's) with Gate Material Engineering," Invited Talk, Texas Instruments, Inc., Dallas, TX, June 18.

 
51. "Compact Threshold Voltage Modeling for Deep-Submicron MOSFET's Based on Numerical Simulation, Empirical Formulation, and Experimental Correlation," Invited Talk, Texas Instruments, Inc., Dallas, TX, June 18, 1998.

 
52. "Compact Threshold Voltage Modeling for Deep-Submicron MOSFET's Based on Numerical Simulation, Empirical Formulation, and Experimental Correlation," Invited Talk, Motorola, Inc., Austin, TX, June 15, 1998.

 
53. "Compact Threshold Voltage Modeling for Deep-Submicron MOSFET's Based on Numerical Simulation, Empirical Formulation, and Experimental Correlation," Invited Talk, Avant! Corp., Fremont, CA, June 12, 1998.

 
54. "Compact Threshold Voltage Modeling for Deep-Submicron MOSFET's Based on Numerical Simulation, Empirical Formulation, and Experimental Correlation," Invited Talk, Advanced Micro Devices, Inc., Sunnyvale, CA, June 11, 1998.

 
55. "Multi-Level TCAD Synthesis Approach to the Design and Optimization of Ultra-Small Transistors," Visiting Researcher Seminar, Advanced Micro Devices, Inc., Sunnyvale, CA, December 15, 1997.

 
56. "Subpicosecond Electrical Pulse Generation by Nonuniform Gap Illumination," Research Seminar, Laboratory for Laser Energetics, University of Rochester, August 21, 1996.

Seminars

1. "Silicon Nanowire Modeling Research," 1st Workshop on Future ICs - A CINTRA Workshop, jointly organized by CNRS-IEMN, Thales, and NTU, Nanyang Technological University, Singapore, 5 July 2007.

 
2. "Bridging bottom-up atomic/quantum-level and top-down device/circuit-level modeling in the nanoelectronics era," 1st EEE6 Workshop on Nanoelectronics, Nanyang Technological University, Singapore, October 1, 2005.

 
3. "Scalable Technology in the Nanoelectronics Era: Top-down versus Bottom-up," 1st NTU Nanotech Symposium, Nanyang Technological University, Singapore, January 29, 2005.

 
4. "Scalable RF CMOS with Unified Regional Compact Model and Subcircuit Expansion Approach," Workshop on Nanoscale CMOS for High Frequency Applications, Institute of Microelectronics, Singapore, April 26, 2004.

 
5. "Technology-Based Predictive Compact Model Development for Next Generation CMOS," Faculty Presentation - SRC Project Review, Chartered Semiconductor Manufacturing, Singapore, April 27, 2004.

 
6. "Unified Regional Approach to Consistent and Symmetric DC/AC Modeling of Deep-Submicron MOSFETs," CNEG lunch-time seminar series, Nanyang Technological University, February 28, 2004.

 
7. "MOSFET Compact I-V Modeling for Deep-Submicron Technology Development," E³ Seminar Series in Microelectronics (µE28) - Focus Workshop on Advanced Semiconductor Technology, Nanyang Technological University, September 13, 1999.

 
8. "Exploring the Novel Characteristics of Hetero-Material Gate Field-Effect Transistors (HMGFET's) with Gate Material Engineering," E³ Seminar Series in Microelectronics (µE26), Nanyang Technological University, September 2, 1999.

 
9. "The Virtual Wafer Fab Technology for the Deep-Submicron ULSI Era," Microelectronics Division Seminar, Nanyang Technological University, February 11, 1998.

 
10. "Subpicosecond Electrical Pulse Generation by Nonuniform Gap Illumination: 2D Numerical Simulation," Microelectronics Center Seminar, Nanyang Technological University, April 16, 1997.

 
11. "Mixed-Signal Multi-Level Circuit Simulation with a Dynamic Delay Model," IC CAD Seminar, Nanyang Technological University, October 17, 1996.

 
12. "Parallel Ensemble Monte Carlo for Device Simulation," Workshop on High Performance Computing Activities in Singapore, National Supercomputing Research Center, September 29, 1995.

 
13. "Subpicosecond Electrical Pulse Generation by Nonuniform Gap Illumination: A Monte Carlo Study," Microelectronics Center Seminar, Nanyang Technological University, April 22, 1994.

 
14. "Implicit Mixed-Mode Circuit Simulation," Microelectronics Center Seminar, NanyangTechnological University, October 9, 1992.

 
15. "Ensemble Monte Carlo Modeling of Compound Semiconductor Devices," Microelectronics Center Seminar, Nanyang Technological University, June 6, 1992.

 
16. "Topics in Modeling and Characterization," Analog Design Automation Research Group Industrial Affiliate Workshop, Rochester, September 21, 1990.

 
17. "Ensemble Monte Carlo Modeling of High-Field Transport and Ultrafast Phenomena in Compound Semiconductors," Electrical Engineering Department Public Lecture, University of Rochester, June 18, 1990.

 
18. "GaAs Device Modeling Using Ensemble Monte Carlo Techniques," University of Rochester - Siemens Corporation Technical Workshop, Rochester, January 1988.

Professional Courses / Tutorials

1. "Unified Compact Model for FinFETs and Nanowire MOSFETs," the 10th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT2010), Tutorial, Shanghai, China, Nov. 1, 2010.

 
2. "Introduction to MOS Transistor Compact Modeling for Technology Development, Device Design, and Circuit Simulation," 5-Day In-House Training Course, Altera Corp. (M) Sdn. Bhd., Penang, Malaysia, August 23-27, 2010.

 
3. "Introduction to MOS Transistor Compact Modeling for SPICE Circuit Simulation," In-House Short Course, Systems on Silicon Manufactoring Co. Pte. Ltd. (SSMC), Singapore, June 22, 2007.

 
4. "Introduction to MOS Transistor Compact Modeling for SPICE Circuit Simulation," In-House Short Course, United Microelectronics Corporation (UMCi), Singapore, June 22, 2006.

 
5. "Introduction to MOS Transistor Compact Modeling for SPICE Circuit Simulation," In-House Short Course, United Microelectronics Corporation (UMCi), Singapore, November 11, 2005.

 
6. "Introduction to MOS Transistor Compact Modeling for SPICE Circuit Simulation," In-House Short Course, Systems on Silicon Manufactoring Co. Pte. Ltd. (SSMC), Singapore, November 7, 2005.

 
7. "Multi-Level Modeling of Deep-Submicron CMOS ULSI Systems," 1-Day Short Course, organized by Center for Continuing Education, Nanyang Technological University, September 2, 2002. (Course Brochure)

 
8. "Mixed Analog-Digital Circuit Simulation: An Implicit Mixed-Mode Solution," Technical Excellence Committee Seminar (1-day in-house course), Thomson Multimedia Pte. Ltd., Singapore, April 19, 1996.

 
9. "Introduction to Process and Device Simulations with TSUPREM-4 and MEDICI,"3-Day In-House Workshop, TECH Semiconductor (Singapore) Pte. Ltd., Singapore, March 11-13, 1996.

 
10. "Introduction to Process and Device Simulations with TSUPREM-4 and MEDICI," 3-Day Public Workshop, jointly organized by National Supercomputing Resource Center and Novotronics Pte. Ltd., National Supercomputing Research Center, Singapore, February 5-7 and 12-14, 1996.

for proposed courses.