IEEE Transactions on Electron Devices, Vol. 45, No. 12, pp. 2546-2548, December 1998.

(Manuscript received May 19, 1998; accepted July 23, 1998)

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A novel hetero-material gate MOSFET intended for integration into the existing deep-submicron silicon technology is proposed and simulated.  It is shown that by adding a layer of material with a larger workfunction to the source side of the gate, short-channel effects can be greatly suppressed without degrading the driving ability.  The threshold voltage roll-off can be compensated and tuned by controlling the length of this second gate.  The new structure has great potential in breaking the barrier of deep-submicron MOSFET's scaling beyond 0.1-µm technologies.

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