Journal of Modeling and Simulation of Microsystems (JMSM), Vol. 1, No. 2, pp. 83-90, 1999.

(Manuscript received in Cambridge, MA, USA, 14th May 1999)

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A unified and consistent representation of logic gates at logic and circuit levels is described based on the subcircuit expansion approach.  A dynamic-delay model is proposed for gate-level timing simulation, which includes the effects of nonlinear capacitive loading, input transition time, and multiple-input triggering on the delay.  It is shown that the approach provides near circuit-level accuracy with gate-level speed and is useful for accurate timing simulation of digital and mixed-signal VLSI circuits.

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