Graduate Students & Research Staff Supervised/Supervising

Research Staff

• Dr. Zhaomin Zhu, Senior Research Fellow, School of EEE, NTU.

Project Title: Compact Modeling for Novel III-V Devices - SMART-LEES.  (Jan. 11, 2013 - )

• Mr. Binit Syamal, Research Associate, School of EEE, NTU.

Project Title: Device Characterization and Process-Design-Kit (PDK) Establishment - GaN-on-Silicon.  (Dec. 15, 2011 - )

• Dr. Siau Ben Chiah, Senior Research Fellow, School of EEE, NTU.

Project Title: SOI Model Validation and Characterization - Ruggedized Electronics.  (May 3, 2011 - Aug. 13, 2013)
Project Title: Device Characterization and Process-Design-Kit (PDK) Establishment - GaN-on-Silicon.  (Aug. 14, 2013 - )

• Mr. Junbin Zhang, Project Officer, School of EEE, NTU.

Project Title: Device Characterization and Process-Design-Kit (PDK) Establishment - GaN-on-Silicon.  (Aug. 22, 2011 - Dec. 31, 2012)

• Dr. Junbin Zhang, Research Fellow, School of EEE, NTU.

Project Title: Device Characterization and Process-Design-Kit (PDK) Establishment - GaN-on-Silicon.  (Jan. 1, 2013 - Aug. 13, 2013)

• Mr. Ramachandran Selvakumar, Research Associate, School of EEE, NTU.

Project Title: Multi-Level Modeling of Nanometer CMOS ULSI Systems.  (Aug. 15, 2008 - May 31, 2009)
Project Title: Compact Model Application to Logic/Circuit Design of Futuristic Probabilistic-CMOS  (June 1, 2009 - Feb. 28, 2010)

 

Present affiliation:

ST Microelectronics Singapore

• Mr. Yafei Yan, Research Associate, School of EEE, NTU.

Project Title: Compact Model Application to Logic/Circuit Design of Futuristic Probabilistic-CMOS  (Nov. 4, 2008 - Aug. 19, 2010)

 

Present affiliation:

AMD Singapore

• Mr. William Chandra, Project Officer, School of EEE, NTU.

Project Title: Compact Model Application to Logic/Circuit Design of Futuristic Probabilistic-CMOS  (Jan. 1, 2009 - Mar. 31, 2010)

• Dr. Zuhui Chen, LKY Post-Doctoral Fellow, School of EEE, NTU.

Project Title: Interface Trap Modeling Using Recombination DCIV and CV Methodologies for MOS Transistor Reliability.  (Aug. 29, 2007 - Aug. 28, 2010)

 

Present affiliation:

Institute of Microelectronics Singapore

• Mr. Ashwin Srinivas, Project Officer, School of EEE, NTU.

Project Title: Multi-Level Modeling of Nanometer CMOS ULSI Systems.  (July 4, 2007 - Jan. 31, 2008)

 

Present affiliation:

IBM India Bangalore, India

• Mr. Guan Huei See, Research Associate, School of EEE, NTU.

Project Title: Multi-Level Modeling of Nanometer CMOS ULSI Systems.  (Jan. 2 - Feb. 29, 2008)
Project Title: Technology-Based Predictive Compact Model Development for Next Generation CMOS.  (Feb. 4, 2004 - June 30, 2006)

 

Present affiliation:

Chartered Semiconductor Manufacturing Ltd. 60 Woodlands Industrial Park D, Street 2 Singapore 738406

• Dr. Zhaomin Zhu, Research Fellow, School of EEE, NTU.

Project Title: Multi-Level Modeling of Nanometer CMOS ULSI Systems.  (Oct. 1, 2007 - June 8, 2008)
Project Title: Compact Modeling and Characterization of Sub-45nm Active and Passive CMOS Devices.  (June 20, 2005 - Sep. 30, 2007)

 

Present affiliation:

Unisantis Electronics Ltd. Singapore 117684

• Mr. Karthik Chandrasekaran, Project Officer, School of EEE, NTU.

Project Title: Compact Modeling and Characterization of Sub-45nm Active and Passive CMOS Devices.  (July 1- Sep. 27, 2006)
Project Title: Technology-Based Predictive Compact Model Development for Next Generation CMOS.  (Jan. 6 - June 30, 2006)
 

Present affiliation:

Advanced Micro Devices, Inc. Sunnyvale, CA 94088 U.S.A.

• Dr. Wangzuo Shangguan, Research Fellow, School of EEE, NTU.  (Mar. 26, 2004 - Dec. 14, 2005)

Project Title: Multi-Level Modeling of Nanometer CMOS ULSI Systems
 

Present affiliation:

National University of Singapore Singapore 119077

• Mr. Siau Ben Chiah, Project Officer, School of EEE, NTU.

Project Title: Technology-Based Predictive Compact Model Development for Next Generation CMOS.  (Jan. 9, 2004 - June 30, 2006)
 

Present affiliation:

Chartered Semiconductor Manufacturing Ltd. 60 Woodlands Industrial Park D, Street 2 Singapore 738406

• Dr. Wensheng Qian, Post-Doctoral Fellow, School of EEE, NTU.

Project Title: Project DOUST: Design and Optimization of Ultra-Small Transistors.
 

Present affiliation:

Shanghai Hua Hong NEC Electronics Co. Ltd. No. 1188 Chuan Qiao Rd., Pu Dong Shanghai, China 201206

• Dr. Hua Shao, Post-Doctoral Fellow, School of EEE, NTU.

Project Title: Project DOUST: Design and Optimization of Ultra-Small Transistors.
 

Present affiliation:

TECH Semiconductor (Singapore) Pte. Ltd. No. 1 Woodlands Industrial Park D, Street 1 Singapore 738799

• Mr. Arjun Ajaykumar, "Compact Modeling of III-V Devices with a Focus on Reliability," Ph.D. candidate.  (starting August 5, 2013)

 
• Mr. Xu Liu, "Transistor/Gate-Level Reliability and Variability Modeling," Ph.D. candidate.  (starting August 5, 2013)

 
• Mr. Binit Syamal, "Compact Modeling for Novel III-V Devices," Ph.D. candidate.  (starting August 6, 2012)

 
• Mr. Hongtao Zhou, "Compact Modeling of High-Voltage Transistors," Ph.D. candidate.  (starting August 7, 2011)

 
• Mr. Ning Ge, "Compact Modeling of EPROM Devices," Ph.D. candidate.  (starting January 24, 2011)

• Mr. Junbin Zhang, "Compact Modeling of High-Voltage (LDMOS/MISHEMT) Devices," Ph.D. Thesis.  (starting August 6, 2007; finished March 2012)

 
• Mr. Shihuan Lin, "Compact Modeling of Gate-All-Arround Silicon Nanowire MOSFETs," Ph.D. Thesis.  (starting January 3, 2006; finished August 2011)

 

Present affiliation:

GLOBALFOUNDRIES Singapore Pte. Ltd. 60 Woodlands Industrial Park D, Street 2 Singapore 738406

• Mr. Zhihuan Wang, "Numerical Characterization of Nanowire Transistors and Logic Gates with Parametric Variations for Probabilistic-CMOS," M.Sc. Dissertation.  (starting August 2009; finished January 2011)

• Mr. Guojun Zhu, "Compact Modeling of Non-classical MOSFETs for Circuit Simulation," Ph.D. Thesis.  (starting January 8, 2007; finished May 2010)

 

Present affiliation:

Systems on Silicon Manufacturing Co. Pte. Ltd. (SSMC) 70 Pasir Ris Industrial Drive 1 Singapore 519527

• Ms. Chengqing Wei, "Characterization and Investigation of Low-Frequency Noise in Emerging CMOS," Ph.D. Thesis.  (starting August 7, 2006; finished May 2010)

 

Present affiliation:

GLOBALFOUNDRIES Singapore Pte. Ltd. 60 Woodlands Industrial Park D, Street 2 Singapore 738406

• Mr. Machavolu Kamakshi Srikanth, "Variability Study of Nanowire: A Compact Model Application," M.Sc. Dissertation.  (starting August 2008; finished July 2009)

 
• Mr. Wei Wang, "Numerical Study of EDMOS Process Integration and Device Design," M.Sc. Dissertation.  (starting August 2008; finished March 2009)

 
• Mr. Guan Huei See, "Scalable Compact Modeling for Nanometer CMOS Technology," Ph.D. Thesis.  (starting December 1, 2004; finished April 21, 2008)

 

Present affiliation:

Chartered Semiconductor Manufacturing Ltd. 60 Woodlands Industrial Park D, Street 2 Singapore 738406

• Mr. Guan Hui Lim, "Development of Statistical Models for Baseband MOSFET Models," M.Eng. Thesis.  (starting July 14, 2005; finished Sep. 2007)

 
• Mr. Karthik Chandrasekaran, "Nanoscale Strained-Si/SiGe and Double-Gate MOSFET Modeling," Ph.D. Thesis.  (starting July 24, 2002; finished Sep. 2006)

 

Present affiliation:

Advanced Micro Devices, Inc. Sunnyvale, CA 94088 U.S.A.

• Mr. Siau Ben Chiah, "Unified AC Charge and DC Current Modeling for Very-Deep-Submicron CMOS Technology," Ph.D. Thesis.  (starting June 28, 2000; finished Dec. 2005)

 

Present affiliation:

Chartered Semiconductor Manufacturing Ltd. 60 Woodlands Industrial Park D, Street 2 Singapore 738406

• Mr. Raymond Selomulya, "Framework Design for Nanometer Technology Development and Transistor Optimization," M.Sc. Dissertation.  (starting August 2003; finished July 2004)

 

Present affiliation:

Agilent Technologies Singapore Pte. Ltd. 1150 Depot Road Singapore 109673

• Mr. William Tan, "Technology Prediciton with Semi-Empirical Compact Modeling Approach," M.Sc. Dissertation.  (starting July 2002; finished June 2003)

 

Present affiliation:

TECH Semiconductor (Singapore) Pte. Ltd. No. 1 Woodlands Industrial Park D, Street 1 Singapore 738799

• Ms. Yuwen Wang, "Predictive Technology Modeling for Deep-Submicron MOSFET Design," M.Eng. Thesis, Nanyang Technological University, 2001.  (Starting June 19, 1999; finished June 18, 2001)

 

Present affiliation:

Chartered Semiconductor Manufacturing Ltd. 60 Woodlands Industrial Park D, Street 2 Singapore 738406

• Mr. Khee Yong Lim, "Design, Modeling, and Characterization of Submicron MOSFETs," Ph.D. Thesis, Nanyang Technological University, 2001.  (Starting August 2, 1997; finished July 31, 2000.  Degree awarded: Sept. 3, 2001)

 

Present affiliation:

Chartered Semiconductor Manufacturing Ltd. 60 Woodlands Industrial Park D, Street 2 Singapore 738406

• Mr. Tianwen Tang, "Mixed-Mode Analog-Digital Circuit Simulation," M.Eng. Thesis, Nanyang Technological University, 1997.  (Degree awarded: July 2, 1997)

 

Present affiliation:

Broadcom Corporation 2099 Gateway Place San Jose, CA 95110 U.S.A.

• Mr. Ye Win Maung, "Modeling and Simulation of the Bias Oscillator Circuit," M.Sc. Dissertation, Nanyang Technological University, Jan. 1999. (Degree awarded: 1999)

 

Present affiliation:

Pulse Engineering, Inc. A Technitrol Company San Diego, CA U.S.A.

• Mr. Xiao Qing Xue, "Macromodeling of a PLL System," M.Sc. Dissertation, Nanyang Technological University, 1996.  (Degree awarded: Nov. 9, 1996)

 

Present affiliation:

Philips, Singapore