Proc. of the 3rd International Conference on Modeling and Simulation of Microsystems  (MSM2000)

San Diego, CA, U.S.A., March 27-29, 2000, pp. 317-320.

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This paper presents a new reverse short channel effect (RSCE) model for threshold voltage modeling of submicrometer MOSFETs. Unlike those conventional empirically-based RSCE models, the proposed model is derived and simplified based on two Gaussian profiles to simulate boron pile-up at the source and drain edges of nMOS devices. The model has a simple compact form that can be utilized to study and characterize the pile-up profile of advanced halo-implant MOSFETs. The analytical model has been applied to, and verified with, experimental data of a 0.25-µm CMOS process for various channel length and substrate bias conditions.

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