A General Approach to Compact Threshold Voltage Formulation Based on 2-D Numerical Simulation and Experimental Correlation for Deep-Submicron ULSI Technology Development

Xing Zhou, Senior Member, IEEE, Khee Yong Lim, Student Member, IEEE, and David Lim


IEEE Transactions on Electron Devices, Vol. 47, No. 1, pp. 214-221, January 2000.

(Manuscript received August 25, 1998; revised July 1, 1999.)


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Abstract

A unified compact threshold voltage model is developed, which accounts for the normal and reverse short-channel effects with full range of body- and drain-bias conditions, and has been verified with experimental data down to 0.18 µm.  The model only has five process-dependent fitting parameters with a simple one-iteration extraction procedure, and can be correlated to process variables for aiding new deep-submicron technology development.  The approach to the model formulation is original and general, and can be extended to other key device performance parameters.


References



Citation

  1. [4] X. Zhou and K. Y. Lim, "A compact MOSFET Ids model for channel-length modulation including velocity overshoot," Proc. 1999 International Semiconductor Device Research Symposium (ISDRS-99), Charlottesville, VA, Dec. 1999, pp. 423-426.
  2. [4] X. Zhou and K. Y. Lim, "A novel approach to compact I-V modeling for deep-submicron MOSFET's technology development with process correlation," Proc. 3rd International Conference on Modeling and Simulation of Microsystems (MSM2000), San Diego, CA, Mar. 2000, pp. 333-336.
  3. [7] K. Y. Lim, X. Zhou, and Y. Wang, "Modeling of threshold voltage with reverse short channel effect," Proc. 3rd International Conference on Modeling and Simulation of Microsystems (MSM2000), San Diego, CA, Mar. 2000, pp. 317-320.
  4. [10] K. Y. Lim and X. Zhou, "A physically-based semi-empirical series resistance model for deep-submicron MOSFET I-V modeling," IEEE Trans. Electron Devices, Vol. 47, No. 6, pp. 1300-1302, June 2000.
  5. [6] X. Zhou, "Mixed-signal multi-level circuit simulation: An implicit mixed-mode solution," (Invited Paper), Proc. National Seminar on VLSI: Systems, Design and Technology (VSDT2000), Indian Institute of Technology, Bombay, India, Dec. 2000, pp. 10-15.
  6. [8] K. Y. Lim and X. Zhou, "A physically-based semi-empirical effective mobility model for MOSFET compact I-V modeling," Solid-State Electron., Vol. 45, No. 1, pp. 193-197, Jan. 2001.
  7. [9] X. Zhou and K. Y. Lim, "Unified MOSFET compact I-V model formulation through physics-based effective transformation," IEEE Trans. Electron Devices, Vol. 48, No. 5, pp. 887-896, May 2001.
  8. [4] X. Zhou, S. B. Chiah, K. Y. Lim, Y. Wang, X. Yu, S. Chwa, A. See, and L. Chan, "Technology-dependent modeling of deep-submicron MOSFET's and ULSI circuits," (Invited Paper), Proc. 6th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT-2001), Shanghai, Oct. 2001, Vol. 2, pp. 855-860.
  9. [7] K. Y. Lim, X. Zhou, and Y. Wang, "Physics-Based Threshold Voltage Modeling with Reverse Short Channel Effect," J. Modeling Simulation Microsystems (JMSM), Vol. 2, No. 1, pp. 51-55, 2001.
  10. [1] K. Y. Lim and X. Zhou, "Compact model for manufacturing design and fuctuation study," Proc. 5th International Conference on Modeling and Simulation of Microsystems (WCM-MSM2002), San Juan, Puerto Rico, Apr. 2002, pp. 746-749.
  11. [2] X. Zhou, "Multi-Level Modeling of Deep-Submicron MOSFETs and ULSI Circuits," (Invited Paper), Proc. of the 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES2002), Wroclaw, Poland, June 2002, pp. 39-44.
  12. [6] X. Zhou, "Mixed-Signal Multi-Level Circuit Simulation: An Implicit Mixed-Mode Solution," (Invited Plenary Paper), Proc. of the 9th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES2002), Wroclaw, Poland, June 2002, pp. 27-31.
  13. [4] R. Rios, W.-K. Shih, A. Shah, S. Mudanai, P. Packan, T. Sandford, and K. Mistry, "A Three-Transistor Threshold Voltage Model for Halo Processes," IEDM Tech. Dig., 2002, pp. 113-116. Download PDF
  14. [13] Y.-S. Pang and J. R. Brews, "Analytical subthreshold surface potential model for pocket n-MOSFETs," IEEE Trans. Electron Devices, Vol. 49, No. 12, pp. 2209-2216, Dec. 2002. Download PDF
  15. [13] A. Mercha, E. Simoen, and C. Claeys, "Impact of the high vertical electric field on low-frequency noise in thin-gate oxide MOSFETs," IEEE Trans. Electron Devices, Vol. 50, No. 12, pp. 2520-2527, Dec. 2003. Download PDF
  16. C. L. Yu, L. A. Yang, and Y. Hao, "A compact I-V model for lightly-doped-drain MOSFETs," Chinese Phys. vol. 13, no. 7, pp. 1104-1109, Jul. 2004.
  17. [17] B. C. Paul, A. Raychowdhury, and K. Roy, "Device optimization for digital subthreshold logic operation," IEEE Trans. Electron Devices, Vol. 52, No. 2, pp. 237-247, Feb. 2005. Download PDF
  18. [16] S. Mukhopadhyay, A. Raychowdhury, K. Roy, "Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile," IEEE Trans. CAD, Vol. 24, No. 3, pp. 363-381, Mar. 2005. Download PDF
  19. [8] P. Su and W. Lee, "Modeling geometry-dependent floating-body effect using body-source built-in potential lowering for SOI circuit simulation," Jpn. J. Appl. Phys., Vol. 44(4B), pp. 2366-2370, Apr. 2005.
  20. [16] A. Agarwal, S. Mukhopadhyay, C. H. Kim, A. Raychowdhury, K. Roy, "Leakage power analysis and reduction: models, estimation and tools," IEE Proc-Computers & Digital Tech., Vol. 152, No. 3, pp. 353-368, May 2005. Download PDF
  21. [16] B. C. Paul and K. Roy, "Oxide thickness optimization for digital subthreshold operation," IEEE Trans. Electron Devices, Vol. 55, No. 2, pp. 685-688, Feb. 2008. Download PDF


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